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| 1/49 september 2001 rev. 01a AN1356 application note psdsoft express and psd4235g2 design guide contents n physical connection n first design example - isp capable system, limited iap C memory map C psdsoft express design entry n second design example C isp, full iap & cpld logic elements C memory map C psdsoft express design entry n third design example C isp and advanced iap C memory map C psdsoft express design entry n conclusion n references easy flash? psd4x35g2 devices are members of a family of flash memory-based peripherals for use with embedded microcontrollers (mcus) or microprocessors (mpus). these programmable system devices (psds) consist of memory, logic, and i/o. when coupled with a low-cost, rom-less mcu/ mpu, the psd forms a complete embedded flash memory system that is 100% in-system-programmable (isp). there are many features in the psd silicon and in the psdsoft express ? development software that make isp easy for you, regardless of how much experience you have in embedded flash memory design. this document offers three designs using an st psd4235g2 and a philips p51xa mcu. note that a variety of 16-bit mcu/ mpus can be used in place of the philips part. although the specifics of this document are based on the p51xa-g30, this document can be used as a guide for other mcu/mpu applications. the first design is a simple system to get up and running quickly for basic applications, or to check out prototype hardware. the second design illustrates the use of concurrent memory operation for field-updates and includes the use of programmable logic. the third design highlights advanced concurrent memory operation. you can start with the first design and migrate to the second and third as your requirements grow. another member of the psd4x35g2 family, the psd4135g2, is a lower cost device with a subset of features of the psd4235g2. see data sheets and an1426 for details. in-system programming and in-application re-programming our industry uses the term in-system programming, or isp, in a general sense. isp is applicable to programmable logic, as well as programmable non-volatile memory (nvm). an additional term is used in this document: in-application re- programming (iap). there are subtle yet significant differences between isp and iap when microcontrollers are involved. isp of memory means that the mcu is off line and not involved while memory is being programmed. iap of memory means that the mcu participates in programming memory, which is important for systems that must be online while updating firmware. often, isp is well suited for manufacturing, while iap is appropriate for field updates. psd4x35g2 devices provide
AN1356 - application note 2/49 both isp and iap. keep in mind that iap can only program the memory sections of the psd, not the configuration and programmable logic portions. isp can program all areas of the psd. the iap problem typically, a host computer downloads firmware into an embedded flash memory system through a communication channel that is controlled by the mcu. this channel is usually a uart, but any communication channel that the mcu supports will do (can, modem, usb, j1850, etc). the mcu must execute the code that controls the iap process from an independent memory array that is not being erased or programmed. otherwise, boot code and flash memory programming algorithms (iap loader code) will be unavailable to the mcu. it is absolutely necessary to use an alternate memory array (an independent memory that is not being programmed) to store the iap loader code. a system designer must choose the type of alternate memory to store iap loader code (rom, sram, flash memory, or eeprom) as each type has advantages and disadvantages. this alternate memory may reside external to the mcu or on-board the mcu. a top-level view of an embedded iap flash memory system with external memory is shown in figure 1. figure 1. embedded flash memory system capable of iap (5 devices) a common solution without a psd device, implementing iap with the p51xa and most other 16-bit mcus can be difficult, expensive, and time consuming. many p51xa designers will use external or internal prom to implement a boot-loader using the p51xa uart to download code from a host computer into p51xa sram (philips application note an97019). p51xa execution then jumps to the sram to execute the remainder of the download process to program flash memory. this is a cumbersome and error prone exercise using re- locatable code in volatile memory which is difficult to debug, vulnerable to power outages, and not supported by all emulators. additionally, it is an expensive task to update the iap loader code that is stored in prom. a better, integrated solution figure 2 shows a two-chip solution using an easy flash psd4235g2. this system has ample main flash memory, a second alternate flash memory to hold the iap loader code and general data, and more sram. all three of these memories can operate independently and concurrently; meaning the mcu can operate from one memory while erasing/writing the other. this allows the mcu to continue normal operation (at possibly a reduced level) during iap, which is crucial for some applications. this system also has programmable logic, expanded i/o, and design security. the two-chip solution is 100% programmable in the factory or in the field. ai04059 embedded system system i/o cpld 16-bit mcu/mpu host computer communication channel main flash memory 256 kbytes alternate memory for iap loader code system sram 8 kbytes 3/49 AN1356 - application note figure 2. embedded flash memory system capable of isp and iap (2 devices) by design, the iap method described above requires mcu participation to exercise a communication channel to implement a download to the main flash memory. the psd4235g2 also offers an alternative method (isp) to program the psd using a built-in ieee-1149 jtag interface requiring no mcu participation. this means that a completely blank psd can be soldered into place and the entire chip can be programmed in-system in just a few seconds using sts flashlink? jtag cable and psdsoft development software. no p51xa firmware needs to be written, just plug in the flashlink? cable to your pc parallel port and begin programming memory, logic, and configuration. this is a powerful feature of the psd4235g2 that allows immediate development of application code in your lab, smart manufacturing techniques, and easy field updates. psdsoft express is available from our website. the availability of the flashlink? cable is also detailed there. lets take a quick look inside the easyflash? psd4235g2, as shown in figure 3. you can see the three independent memory arrays, which are selected on a segment basis when the proper mcu address is decoded in the decode pld. the page register participates in memory decoding, which greatly simplifies paging. the mcu address, data, and control signals are routed throughout the chip and can be used within the complex pld (cpld). the cpld has 16 output microcells (omcs), each containing a flip-flop and combinatorial logic. the cpld also has 24 input microcells (imcs) used for conditioning incoming signals. the mcu has direct memory-mapped access to both omcs and imcs. additionally, the cpld contains 8 programmable external chip-select outputs. there are 52 i/o pins that can be individually configured for many different functions. a power management scheme can selectively shut down parts of the chip and tailor special power saving mechanisms on-the-fly. the security feature can block access to all areas of the chip from a device programmer/reader. finally, the self-contained jtag-isp controller allows programming of all areas of the chip. in the second design example of this document, you will see how to use the cpld to implement a loadable counter, a state machine, combinatorial logic, and other functions using omcs, imcs, the page register, and external chip-selects. ai04060 embedded system system i/o jtag isp 16-bit mpu/mcu host computer communication channel 512 kbyte flash 32 kbyte flash 8kbyte sram programmable logic i/o psd4x35g2 AN1356 - application note 4/49 figure 3. top level block diagram of psd4235g2 physical connection connect your p51xa to the psd4235g2 as shown in figure 4. the jtag programming channel, lcd module, system i/o, mcu i/o signals, and battery back up are optional. they are present in this application note to illustrate psd functions. there are four unused psd i/o pins in this example. unused pins should be pulled to vcc with a 100k resistor or tied to gnd. also, see application note 54 for more information on the jtag-isp connection options. ai04068 jtag controller cpld 16 output microcells (omc), 24 input microcells (imc) 512 kbyte primary flash 8 segments decode pld 8 kbyte sram 32 kbyte second flash 4 segments page reg power mngt mcu address / data pld bus i/o bus i/o port a mcu address / data / control bus psd4235g2 mcu control device security 8 external chip-selects i/o port b i/o port c i/o port d i/o port e i/o port f i/o port g 5/49 AN1356 - application note figure 4. physical connections, p51xa and psd4x35g2 note: pullup (100k) or ground all unused inputs. p51xa internal bus control register settings for 70ns pf0 ai04071 pf1 pf2 pf3 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 a1 a2 a3 a4/d0 a5/d1 a6/d2 a7/d3 a8/d4 a9/d5 a10/d6 a11/d7 a12/d8 a13/d9 a14/d10 a15/d11 a16/d12 a17/d13 a18/d14 a19/d15 xtal1 xtal2 p1.6/t2 p1.7/t2ex p3.4/t0 p1.4/rxd1 p1.5/txd1 p3.0/rxd0 p3.1/txd0 p3.2/!int0 p3.3/!int1 p3.5/t1/busw p1.1/a1 p1.2/a2 p1.3/a3 p0.0/a4d0 p0.1/a5d1 p0.2/a6d2 p0.3/a7d3 p0.4/a8d4 p0.5/a9d5 p0.6/a10d6 p0.7/a11d7 p2.0/a12d8 p2.1/a13d9 p2.2/a14d10 p2.3/a15d11 p2.4/a16d12 p2.5/a17d13 p2.6/a18d14 p2.7/a19d15 cntl0 (!wr) cntl1 (!rd) cntl2 (!psen) pd0 (ale) pd1 (clkin) pd2 (!csi) pd3 (!wrh) _wrl _rd _psen ale _wrh p3.6/!wrl p3.7/!rd !psen ale/!prog p1.0/a0/!wrh !reset _reset !rst p51xa-g30 psd4235g2-70 !ea/v pp /wait uart port0 uart port1 up to 27 mhz pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 2 x 16 lcd module data bus e r/w rs lcd_e lcd_rw lcd_a0 zero sys-ready sequence_ok strobed_in_0 strobed_in_1 strobed_in_2 strobed_in_3 strobed_in_5 strobed_in_6 strobed_in_7 strobed_in_4 pc7 pf4 pf5 pf6 pf7 mcuio_pf5 mcuio_pf6 mcuio_pf7 mcuio_pf4 pc1 pc2 pc4 pc5 pc6 mcuio_pc0 mcuio_pc1 mcuio_pc2 mcuio_pc3 mcuio_pc5 mcuio_pc6 mcuio_pc7 mcuio_pc4 pc3 pg0 pg1 pg2 pg4 pg5 pg6 pg7 mcuio_pg0 mcuio_pg1 mcuio_pg2 mcuio_pg3 mcuio_pg5 mcuio_pg6 mcuio_pg7 mcuio_pg4 pg3 pe0 (tms) pe1 (tck) pe3 (tdo) pe4 (tstat) pe5 (!terr) tms tck tdi tstat _terr tdo pd2 (tdi) jtag-isp connector pe6 (v stby ) pe7 (v baton ) system_reset system_clock v cc 3.6v lithium battery + general purpose i/o general purpose i/o general purpose i/o system inputs system outputs system inputs system outputs !rst d0-d7 v cc v cc v cc 10k 4.7k 4.7k AN1356 - application note 6/49 first design example - isp capable system, limited iap the first design example is capable of isp and limited iap. it outlines the steps required to get a flash memory p51xa system up and running quickly. the 32 kbytes of psd secondary flash memory will be programmed with p51xa firmware (over the jtag-isp channel) that will execute low-level system hardware tests. this firmware is also able to access 512 kbytes of main psd flash memory, used as data only not program space. this provides a way to develop code to erase and write to main psd flash memory while executing from secondary flash memory. the second and third design examples take full advantage of concurrent memory operation and iap, by allowing program execution from main flash memory in addition to writing to it. you should become familiar with this first design before using the second and third. memory map for this first simple design, a psd4235g2 is used with the following memories: n 512 kbytes main flash memory, broken into eight 64 kbyte segments denoted fs i (i = 0-7) n 32 kbytes secondary flash memory, broken into four 8 kbyte segments denoted csboot j (j = 0-3) . n 8 kbyte sram denoted rs0 n 256-byte psd4235 control registers denoted csiop. note: psd memory segment address locations are defined using psdsoft express ?. well use the psds secondary flash memory to hold the boot code, p51xa interrupt vectors, hardware drivers, and common functions including routines that erase/program main psd flash memory. for this example, well execute from the psds secondary flash memory only and use the psds main flash memory as data. see the memory map in figure 5. 7/49 AN1356 - application note figure 5. memory map: simple p51xa/psd4235g2 design note: 1. p51xa firmware gets programmed here by jtag-isp or conventional programmer tool. psdsoft express design entry highlights of design entry are given here. follow along using psdsoft express if you wish. open a new project n invoke psdsoft express . n create a new project. n select your project folder and name the project (in this example, name the project simplexa in the folder psdexpress\my_project). n select an mcu. in this example, were using a philips p51xag3x. n select /wrl, /rd, /psen, /wrh, burst mode for the control signals. n select the psd4000 series for the psd family. n select a psd4235g2 and use the 80-pin tqfp package (u package). n based on the above selections, the mcu bus will be automatically set to 16-bits multiplexed. n select the main psd flash memory to reside in data space upon power-up. 8ffffh 08000h 8ffffh 80000h 06000h - 07fffh 04000h - 05fffh 7ffffh 0ffffh 5ffffh 70000h 50000h 30000h 3ffffh ai04072 fs0 64k bytes psd main flash nothing mapped csboot0, 8kb psd 2nd flash csboot3, 8kb psd 2nd flash p51xa program space p51xa data space (note 1) fs7 64k bytes psd main flash fs6 64k bytes psd main flash fs5 64k bytes psd main flash fs4 64k bytes psd main flash fs3 64k bytes psd main flash fs2 64k bytes psd main flash fs1 64k bytes psd main flash 10000h nothing mapped csiop, psd cnti regs rs0, 8k bytes psd sram nothing mapped lcd_e, ext lcd chip sel p51xa-g3 regs/sram 6ffffh 60000h 4ffffh 40000h 2ffffh 20000h 0a000h 08000h - 09fffh 07000h - 070ffh 06000h - 06001h 00400h - 05fffh 00000h - 003ffh 1ffffh 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes csboot1, 8kb psd 2nd flash csboot2, 8kb psd 2nd flash 02000h - 03fffh 00000h - 01fffh AN1356 - application note 8/49 n select the secondary psd flash memory to reside in program space upon power-up. the selection of program space or data space for the flash memories determines whether or not the p51xa signals, psen or rd respectively, will activate the output enables of the indivi dual psd flash memory arrays upon power up. you will learn in the second and third designs that this setting can be changed by mcu firmware at runtime to implement iap. note that this applies only to mcus with the harvard architecture (separate address spaces for code and data). for mcus with von nueman architecture (a single linear address space for code and data), the menu choice for program and data space does not apply and does not appear. now you have your project established based on a psd4235g2 and a p51xag3. the psd will be compatible with the burst mode feature, unique to the p51xa, meaning that the special use of the lower four non-multiplexed address bits (a0..a3), the shifting of the upper address bits ( a4..a19 ), and opcode reads with no ale pulse are automatically supported by the psd. although this document uses the philips p51xa as a detailed example, the methods and examples within are very similar for other mcu/mpus. psd silicon adapts to many different mcu/mpu interfaces automatically based on selections in psdsoft. mcu and psd selection this is what the screen should look like after youve made the selections: figure 6. mcu and psd selection 9/49 AN1356 - application note click ok . now you will be asked if you want to use the design assistant, extended design assistant, or a example template as shown: figure 7. design assistant selection choose design assistant. this will help you become familiar with most of the flow of psdsoft express . well use the extended design assistant in the second design example. for any of the three choices, abel hdl statements are automatically generated for you behind-the- scenes based on your point-and-click design entry. these statements include pin, node, and signal declarations as well as logic equations. the design assistant choice does not allow editing access * to these generated abel statements, which is typically not necessary for simpler designs. it is sometimes necessary to edit or add statements to the generated abel file for more complicated pld designs that use counters, shift registers, state machines, etc. in these cases, the extended design assistant should be chosen, allowing you to add abel statements in designated sections of the generated file that will not be affected by subsequent design iterations in the point-and-click entry environment. you will learn how to do this in design number two. in future designs you may choose to use a pre-defined example template , which will make many of the choices for you based on your selection of mcu and psd you just have to tailor the template to fit your design. but again, there is no ability to edit hdl language statements * . use this mode to get a suggested memory map from st based on the mcu/mpu and psd combination that you have chosen. note that not all mcu/mpu selections will produce a choice for a pre-defined example template in which case only two choices will be available: the design assistant and extended design assistant. * at a later point in your design cycle, regardless of which of the three methods you have chosen, you may optionally turn on the ability edit abel equations. well see how to do this in the second design example. note that this is not available for the psd9xxf and psd4135g2 devices that have a simple pld section. pin definitions next you are taken to the pin definitions screen, which allows you to define each psd pin function one- by-one on a point-and-click basis. notice that the psd pins connecting to the mcu are already defined for you because their function is fixed. for this first simple design, you need only to define a few pins that are listed below. in the second design example we use all of the signals shown in the schematic of figure 4. n define an active-high chip select output on port b pin pb0. choose external chip select C active-hi from the cpld output section and name it lcd_e. click add . AN1356 - application note 10/49 n define a combinatorial cpld output on port b pin pb1. choose combinatorial from the cpld output section and name it lcd_rw. click add . n define a combinatorial cpld output on port b pin pb2. choose combinatorial from the cpld output section and name it lcd_a0. click add . n define an additional jtag-isp pin on port e pin pe4. choose dedicated jtag C tstat from the other section. click add . notice the name tstat is automatically included. also notice that the signal _terr is automatically added to port e pin pe5. these two signals work together as a pair to reduce jtag-isp programming time by 10% C 15%. see application note 54 on our web site for details. n define a pin to accept a battery voltage input for psd sram on port e pin pe6. choose sram standby voltage input from the other section. click add . the name vstby is automatically included. your pin definition screen should now look like the screen capture below: 11/49 AN1356 - application note figure 8. pin definition screen you can view a summary of your pin definitions by clicking the view button. when you are satisfied that you have defined all the pins correctly, click the next>> button to be taken to the page register definition screen as shown next. page register definition since 16-bit mcus have an abundant number of address lines, memory paging is rarely needed for these mcus. however, the psd page register bits can be used for logic as well. you will learn how to do this in the second design example. AN1356 - application note 12/49 figure 9. page register definition for this simple design, click next >> or click on the chip select equations tab. chip select equations (system memory map) now that the psd pins are defined, you will need to define the system memory map. this is accomplished by defining all the chip-selects in the system (both internal to the psd and external chip-selects). the three memories inside the psd are individually selected segment-by-segment when mcu addresses are presented to the decode pld (dpld). each internal psd memory segment has its own individual chip-select name. for example, the main psd flash memory has eight individual chip-selects (one for each sector) named fs0 C fs7. see the psd4235g2 data sheet for details. each psd memory segment must be defined in psdsoft express if it is to be accessed by the mcu. we must define the internal psd memory segment chip-selects: fs0 to fs7, csboot0 to csboot3, rs0, and csiop to match the memory map of figure 5. the external chip-select for the lcd module, lcd_e, must also be defined, as shown in figure 5. your screen should look like the following: 13/49 AN1356 - application note figure 10. chip select equations start with the internal chip-select for the psd sram, which is rs0. looking at the memory map of figure 5, we see that 8 kbytes (4 kwords) of address space needs to be allocated to the psds internal sram. so, we enter the start address of 8000h and the end address of 9fffh as shown above. notice that you do not have to qualify the rs0 chip-select with any mcu control signals (_rd, _wrh, _wrl, _psen, etc) because that is taken care of in silicon, just type in the addresses. this is true for all chip-selects of internal psd memory no mcu control signal qualifiers are necessary. also notice that the page number selection is grayed out since we defined no page register bits in the previous screen. next, define the chip-select for the internal psd control registers by clicking on csiop on the left side of the screen. enter its address range as shown: figure 11. csiop address range continue to define internal psd memory chip-selects for the main flash memory segments fs0 to fs7, and then secondary flash memory segments csboot0 to csboot3. use figure 5 as a guide for address ranges. AN1356 - application note 14/49 again, no signal qualifiers are needed for internal psd memory chip-selects. here are a few examples of what the screen should like for these chip-selects: figure 12. fs0 address range figure 13. fs1 address range figure 14. fs7 address range figure 15. csboot0 address range 15/49 AN1356 - application note figure 16. csboot7 address range finally, define the external chip-select for the lcd module, lcd_e. this chip-select is different for two reasons. first, it is an external chip-select that does not activate any memory element inside the psd because the signal lcd_e is output on a psd i/o pin. and second, this chip-select requires qualifiers, meaning that this logic signal is true only for a given mcu address range and only when one of two other another signals are active. in this design, lcd_e is true only when the mcu presents an address in the range of 06000 to 06001h and when either the p51xa control signal _wrl is true, or when p51xa signal _wrh is true. to create this logic, enter information as shown in the screen below. since both signals, _wrl and _wrh, are active low as they leave the p51xa, the logical not operator (!) is used when they are specified as qualifiers. signal qualifiers may be added by parking the cursor where you want the signal name to go then just double-click on the signal name in the list of eligible signals. figure 17. signal qualifiers you can click the view button at any time to see a summary. once you are satisfied with the results, click the next >> button. AN1356 - application note 16/49 i/o logic equations now define the two combinatorial output signals lcd_rw and lcd_a0. you should see the following screen: figure 18. i/o logic equations the signal lcd_rw should be a constant 0 volt output, so highlight the signal lcd_rw in the list of signals box on the left. then park your cursor in the enter logic equation box at the upper left corner. now scroll down in the eligible signals box until you find the signal gnd. double-click on gnd and it will appear in the logic equation box as shown above. this is how you create equations for each of the i/o signals. you can also type the equations into the box. now set the output enable term for the signal lcd_rw to always active, or vcc as shown: figure 19. lcd_rw equation next, define the signal lcd_a0 as shown below: 17/49 AN1356 - application note figure 20. lcd_a0 equation to do this, park your cursor in the enter logic equation box, then go to the valid operators box, and double-click on the ! symbol. now go to the eligible signals box and double-click on _wrh. lastly, set the output enable term for lcd_a0 to vcc just like lcd_rw. as an example of more complex logic, you can implement longer equations by adding signals and operators as shown in the following generic logic statement: figure 21. generic logic statement notice that you can include other output signals (feedback) as part of the equation. there are no user-defined nodes in this simple design example, so click done . this starts a preliminary resource and system check of the information you have entered. analysis is performed to check for overlapping memory segments, problems with synthesizing the logic, and other problems. any errors encountered will be indicated. an abel hdl file is generated. design flow once you have clicked on done , you are taken to the design flow window. use this window as your main navigational tool for psdsoft express ?. clicking on individual boxes within the flow diagram will invoke a process. a box shadowed in red identifies the next process that needs to be completed. the first three steps have been completed to this point. if you invoke a process that invalidates other processes downstream, the gray boxes indicate which processes must be invoked again and the red shadow indicates which process to invoke first. the design flow should be in the following state: AN1356 - application note 18/49 figure 22. design flow additional psd settings click the additional psd settings box. this is where you may choose to set the security bit to prevent a device programmer from examining or copying the contents of the psd. you can also click through the other sheets on this screen to set the jtag ieee 1149.1 usercode value and set sector protection on individual psd non-volatile memory segments as desired. fit design to silicon click the fit design to silicon box. psdsoft express will input the generated abel file and all other configuration settings to synthesize the logic, creating reduced logic equations and a fusemap that fits the psd4235g2 silicon elements. when this process is complete, a report will pop up that shows the resulting pin assignments and the resulting reduced equations. this is the fitter report, which you can use to document your design. psd-specific c code generation you can take advantage of the provided low-level c code drivers for accessing memory elements within the psd by clicking on the generate c code specific to psd box in the design flow window. ansi c code functions and headers are generated for you to paste into your c compiler environment. simply tailor the code to meet your system needs and compile. c code generation can be performed anytime after a project is opened. to generate ansi c functions and headers, simply specify the folder(s) in which you want the header files and the c source file to be written, and name the c source file. select the categories of functions that you would like to include, then click generate . three files will be written to your specified folder(s): 19/49 AN1356 - application note n AN1356 - application note 20/49 figure 23. merge mcu firmware in the left column are individual psd memory segment chip-selects (fs0, fs1, and so on). the next column shows the logic equations for selection of each internal psd memory segment. these equations reflect the choices that you made while defining psd internal chip-select equations in an earlier step. in the middle of the screen are hexadecimal start and stop addresses that psdsoft express has filled in for you based on your chip-select equations. on the right are fields to enter (browse) the mcu firmware files. select intel hex record for record type as shown. select direct for mapping mode. this maps the mcu addresses residing inside the hex file directly to the corresponding addresses within the range of the file start and stop addresses that are typed into the boxes. direct is the most typical setting. relative mode will place contents of the specified hex file starting at the beginning of a physical psd memory segment, in other words, no offset from the base of the physical memory segment. relative is used only for very unique applications. scroll all the way down to the bottom to get to the secondary flash memory. now, click browse for csboot0 and select the firmware file, psdexpress\examples\boot_32k.hex. repeat for csboot1, csboot2, and csboot3 specifying this same file name for each. once you have filled in the file names, your screen should look like the one below: 21/49 AN1356 - application note figure 24. scroll to the bottom to get to the secondary flash memory this specification places firmware in psd secondary flash memory segments csboot0 through csboot3. psdsoft express will extract any firmware that lies inside the file boot_32k.hex between mcu addresses 0000 and 7fff and place it in appropriate psd memory segment. click ok to generate the composite object file, simplexa.obj. note: the file boot_32k.hex does not contain p51xa firmware. it is used to illustrate the firmware merging process. boot_32k.hex has a data pattern for each of the four segments of secondary psd flash memory. csboot0 will receive aah, csboot1 receives bbh, csboot2 receives cch, and csboot3 receives ddh. the point is that although only one file name was specified for four different psd memory segments, psdsoft express extracted the proper data for each segment based on the specified file start and stop addresses and the addresses contained inside the file boot_32k.hex. you may examine the contents of the file boot_32k.hex if you wish to better understand. programming the psd the file simplexa.obj can be programmed into the psd by one of three ways: n the st flashlink? jtag cable, which connects to the pc parallel port. n the st psdpro device programmer, which also uses the pc parallel port. n third-party programmers, from stag, bp micro, and others. see our website at www.st.com for list (psd products, programming, then programmers). scroll to the bottom bottom to get to the secondary flash memory AN1356 - application note 22/49 programming with flashlink? connect the flashlink? jtag-isp cable to your pc parallel port. click the jtag-isp box in the design flow window. you will be asked how many devices are in your jtag chain. for this example, select only one. you would only select more than one if you had more than one isp device in your jtag chain (even non-st jtag devices may be included in the chain). you may choose to disable this question that appears each time you enter the jtag screen, and then turn it back on later using the preferences menu choice from the project pull-down menu. click ok after your selection, you should see the following screen: figure 25. jtag chain setup window this window enables you to perform jtag-isp operations and also offers a loop back test for your flashlink ? cable. if this is your first use, test your flashlink? cable and pc parallel port by clicking the hw setup button, then click looptest button and follow the directions. now lets define our jtag-isp environment. psdsoft express should have filled in the folder and filename of the object file to program, the psd device, and the jtag-isp operation, as shown in the screen above in step 1. for this design example, we have chosen to use all six jtag-isp pins (instead of four) so six pins is automatically filled in. using all six pins reduces programming time by 10%-15%. refer to application note 54 for details. to begin programming, connect the jtag cable to the target system, power-up the target system, and click execute on the jtag screen in step 2. the log window at the bottom of the jtag screen shows the progress. you can choose to save all log messages to a file by clicking the log mode box. there are optional choices available when the properties button is clicked. one choice includes setting the state of all non-jtag psd i/o pins during jtag-isp operations (make them inputs or outputs). the default state of all non-jtag psd i/o pins is input, which is fine for this design example. the other 23/49 AN1356 - application note choice allows you to specify an ieee 1149.1 usercode value to compare before any jtag-isp operation starts. this is typically used in a manufacturing environment. see the on-screen description for details. after jtag-isp operations have completed, you can save the jtag setup for this programming session to a file for later use. to do so, click on the save button in step 3. to restore the setup of a previous session, click the browse button in step 3. programming with psdpro connect the psdpro device programmer to your pc parallel port per the installation instructions. click on the conventional programmers box in the design flow window. you will see this: figure 26. parallel programming window if this is the first use of the psdpro, youll need to designate the psdpro as the device connected to your parallel port. to do this, click the set h icon button at the top of the conventional programming screen and choose the psdpro. then click on the h test icon to perform a test of the psdpro and the pc parallel port. after testing, place a psd4235g2 into the socket of the psdpro and click on the program icon. (the simplexa.obj file is automatically loaded when this process is invoked.) the messaging of psdsoft will inform you when programming is complete. this window is also helpful even if you do not have a psdpro device programmer. use this window to see where the merge mcu firmware utility has placed mcu firmware within physical memory of the psd. for this design example, click on the secondary psd flash memory icon fb in the tool bar. you can see the aah pattern in csboot0 from the file boot_32k.hex. scroll down to the beginning of csboot1 (address 82000) and see the bbh pattern, and so on. this is useful when you want to examine your own firmware. to see how all of the mcu absolute addresses translated into direct physical psd memory addresses, view the report that psdsoft generates under reports from the main toolbar, then select address translation report. within the report, the start and stop addresses are the absolute mcu system addresses that you have specified. the addresses shown in square brackets in the reportare the direct physical addresses used by a device programmer to access the memory elements of the psd in a linear fashion (a special device programming mode that the mcu cannot access). AN1356 - application note 24/49 second design example C isp, full iap & cpld logic elements this second design example builds upon the first by adding true iap capability. you will see how to execute from secondary psd flash memory in program space while programming the main psd flash memory in data space, then move main psd flash memory to program space for execution. we will also create some complex logic in the cpld requiring use of the extended design assistant. memory map figure 27 and figure 28 represent the system memory maps for this design. figure 27 represents the system memory map at power-up and after reset. this map is also valid during iap. notice that all of the main psd flash memory is initially in data space so that the p51xa can write to it during iap. also notice that all of the secondary psd flash memory is initially in program space so the p51xa can execute code from it during iap. the choice for this initial placement of memory in program or data space was made within psdsoft express (define mcu and psd in flow diagram). figure 28 represents the system memory map after iap is complete. all of main psd flash memory has moved to program space. the psd has a control register (named the vm register) that allows the p51xa to change the definition of program space and data space at run-time for iap purposes. this vm register is accessed at an address offset from the base address, csiop. sequence of events for iap: n figure 27 - at power on or after reset, the p51xa boots from secondary psd flash memory n figure 27 C p51xa runs a checksum of the main psd flash memory in data space n figure 27 - if needed, p51xa programs and verifies main psd flash memory in data space via the uart n figure 27 C p51xa writes 06h to the vm register to place main psd flash memory into program space n figure 28 C main flash memory has moved to program space as a result of writing 06h to vm register n figure 28 C p51xa can now execute application code from either main or secondary psd flash memory to accomplish this iap function, no chip-select equations have to change from the first simple design example. only the vm register must be accessed at run time as described above. for mcus/mpus without harvard architecture (harvard: separate program and data address spaces) the vm register is not needed since there is only one address space for both code and data. iap is much simpler for these mcus/mpus. 25/49 AN1356 - application note figure 27. memory map at boot-up or reset and during iap note: 1. psd vm register initially 12h, main psd flash memory in data space. 2. iap loader code gets programmed here by jtag-isp or conventional programmer tool. 8ffffh 08000h 8ffffh 80000h 06000h - 07fffh 04000h - 05fffh 7ffffh 0ffffh 5ffffh 70000h 50000h 30000h 3ffffh ai04081 fs0 64k bytes psd main flash nothing mapped csboot0, 8kb psd 2nd flash csboot3, 8kb psd 2nd flash p51xa program space p51xa data space (note 2) fs7 64k bytes psd main flash fs6 64k bytes psd main flash fs5 64k bytes psd main flash fs4 64k bytes psd main flash fs3 64k bytes psd main flash fs2 64k bytes psd main flash fs1 64k bytes psd main flash 10000h nothing mapped csiop, psd cnti regs rs0, 8k bytes psd sram nothing mapped lcd_e, ext lcd chip sel p51xa-g3 regs/sram 6ffffh 60000h 4ffffh 40000h 2ffffh 20000h 0a000h 08000h - 09fffh 07000h - 070ffh 06000h - 06001h 00400h - 05fffh 00000h - 003ffh 1ffffh 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes csboot1, 8kb psd 2nd flash csboot2, 8kb psd 2nd flash 02000h - 03fffh 00000h - 01fffh AN1356 - application note 26/49 figure 28. memory map just after p51xa writes 06h to psd vm register note: 1. iap complete, main psd flash memory moves to program space your system design may require that you operate application code completely from main psd flash memory after iap is complete. this means swapping the secondary psd flash memory (containing iap loader code) out of program space, and replacing it with main psd flash memory (containing application code). this is explained in the third design example. psdsoft express design entry we are finished with iap issues, now lets get started on the advanced cpld logic design. invoke psdsoft express , open the project simplexa from the first design example (if not already open). pull down project from the menu at the top of the screen, and select save as. for this second design example, save the first project under the new name logicxa. for this second design, logicxa we want to use the extended design assistant environment so go to the project menu pull down at the top of the screen and select preference. then enable abel editing by clicking the box as shown, then ok . 8ffffh 08000h 8ffffh 06000h - 07fffh 04000h - 05fffh ai04082 csboot2, 8kb psd 2nd flash csboot3, 8kb psd 2nd flash p51xa program space p51xa data space nothing mapped csiop, psd cnti regs rs0, 8k bytes psd sram nothing mapped lcd_e, ext lcd chip sel p51xa-g3 regs/sram 0a000h 08000h - 09fffh 07000h - 070ffh 06000h - 06001h 00400h - 05fffh 00000h - 003ffh fs0 64k bytes psd main flash fs7 64k bytes psd main flash fs6 64k bytes psd main flash fs5 64k bytes psd main flash fs4 64k bytes psd main flash fs3 64k bytes psd main flash fs2 64k bytes psd main flash fs1 64k bytes psd main flash nothing mapped 80000h 7ffffh 0ffffh 5ffffh 70000h 50000h 30000h 3ffffh 10000h 6ffffh 60000h 4ffffh 40000h 2ffffh 20000h 1ffffh 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes csboot1, 8kb psd 2nd flash csboot0, 8kb psd 2nd flash 02000h - 03fffh 00000h - 01fffh 27/49 AN1356 - application note figure 29. design assistant selection you should see the full flow diagram as shown below. this flow also appears if extended design assistant is chosen for a new design. note that the ability to edit the abel file is not available for psd9xxf or psd4135g devices, both of which have simple plds (no registers). figure 30. design flow additional box AN1356 - application note 28/49 for this second design example, well implement the following logic elements to illustrate psd functionality: n 4-state state machine with comparator feature. n eight debounced inputs used for state machine input. n 4-bit reloadable down-counter with initial value set by the mcu. n simple clock divider circuit. n 20 general purpose i/o pins controlled by mcu firmware. n psd page register. n miscellaneous combinatorial logic. the general tactic is to use the graphic user interface (gui) of the designs assistant as much as possible to create these logic functions before we have to manually edit the generated abel hdl file. you will see that the gui creates all of the necessary pin and signal declaration statements as well as some of the simple logic equations. after this point, we will open the abel file and add more abel statements to implement the state machine and down-counter. pin definitions to achieve this, lets go back and define the remaining pin functions from the schematic of figure 4. click on the define psd pin/node function box and add the following signals: n define eight inputs on port a that are clocked (sampled) as they enter the psd. choose product term (pt) clocked register from the cpld input section, and name them strobed_in_0 through strobed_in_7. in silicon, these are imcs. n define a combinatorial cpld output on port b pin pb5. choose combinatorial from the cpld output section and name it zero. click add . n define a logic input to the cpld on port b pin pb6. choose logic or address from the cpld input section name it sys_ready. click add . n define a combinatorial cpld output on port b pin pb7. choose combinatorial from the cpld output section and name it sequence_ok. click add . n define eight mcu general purpose i/o signals on port c. the mcu can set these pins to logic high or low as outputs, or read the pins as inputs all through firmware at runtime. to set this up, choose mcui/ o mode from the other section and name them mcuio_pc0 through mcuio_pc7. n define four mcu general purpose i/o signals on port f. choose mcui/o mode from the other section and name them mcuio_pf4 through mcuio_pf7. n define eight mcu general purpose i/o signals on port g. choose mcui/o mode from the other section and name them mcuio_pg0 through mcuio_pg7. n define a common psd clock signal input on port d pin pd1. choose common clock input, clkin in the other section. your screen should look like this: 29/49 AN1356 - application note figure 31. pin definition screen click next>> . page register this brings you to the psd page register definition screen. although we will not need to page memory since this mcu has plenty of address lines, we will use one of the page register bits for general logic. in this case, we define one page register bit as logic and name it begin. this will be used in our state machine to allow it to start cycling. using page register bits saves the use of omcs.all page register bits are available as cpld inputs. note that the page register bits are cleared upon power-up and subsequent resets. define the begin bit as follows, then click next >> . AN1356 - application note 30/49 figure 32. page register definition i/o logic equations there are no changes needed to the memory map (chip-selects) from the first design as all iap enhancements can be accomplished by using the vm register in this case. click next >> to skip the chip select equations screen. you should see the i/o logic equations screen as follows: 31/49 AN1356 - application note figure 33. i/o logic equations notice the eight strobed inputs. these are input micro-cells (imcs), which offer a flip-flop on each of these input pins. for this example, we will define the clock to strobe these imcs on the opposite edge of the state-machine clock. this will guarantee that a stable value is presented to the state-machine. do this by parking the cursor in the enter logic equation box, double-click the ! symbol in the valid operators box, then double-click clkin. it should look like the figure above. repeat this for all eight inputs. the signals lcd_rw and lcd_a0 should already be defined from the first design. the logic for the signals zero and and sequence_ok will be defined when we type in logic while editing the generated abel hdl file, so leave them blank. however, define their output enable signals so they are always on by assigning v cc . thats all we need to do so click next >> . user-defined node equations in this final screen of the design assistant, we define internal logic nodes, both combinatorial and registered. your screen should look like this: AN1356 - application note 32/49 figure 34. user-defined node equations lets establish all of the internal nodes used for this second design. they are: n two register nodes for a 4-state state-machine state_bit_0 and state_bit_1 n one register node for a simple clock divider half_clkin n four register nodes for a down-counter down_count0 to down_count3 n four register nodes to pre-load the down-counter init_count0 to init_count3 n one combinatorial node used as an intermediate node for down-counter term_count each internal node, either combinatorial or registered, will consume one output microcell (omc). first well define two registers to implement a 4-state state machine. click on def node enter the name state_bit_0 and designate it as a register as shown here: 33/49 AN1356 - application note figure 35. define node window now click add . do the same for state_bit_1. you should have the following entries in the list of signals box. figure 36. list of signals you can see that for each register node that is included, its input, clock, reset, and preset values are automatically added to the list. equations can be specified for all of these elements. figure 37 illustrates the relationship between a registered node and its signal names for this example. AN1356 - application note 34/49 figure 37. internal register node and associated signal names continue to add nodes. enter the following node names and node types, clicking add after each: down_count0 register down_count1 register down_count2 register down_count3 register init_count0 register init_count1 register init_count2 register inti_count3 register term_count combinatorial next we will specify equations for as many of these nodes as we can using the design assistant gui. afterwards, we will manually edit the generated abel statements to finish the logic. lets start with the state machine nodes. we wont specify logic for the node inputs using the gui because that will be done when the state machine statements are added to the abel file. so leave it blank as shown here (same for state_bit_1): figure 38. list of signals however, lets assign the clock for each state machine node as clkin: ai04083 state_bit_0 set pre state_bit_0 clock q clr d state_bit_0 state_bit_0 reset leave blank 35/49 AN1356 - application note figure 39. list of signals assign the reset for each state machine node as !_reset: figure 40. list of signals assign the preset for each state machine node to be gnd figure 41. list of signals now lets implement the logic for the simple clock divider circuit shown in figure 42. figure 42. simple clock divider ai04064 gnd pre clkin q clr d half_clkin gnd 1/2 freq of clkin AN1356 - application note 36/49 to do this, make these logic assignments for the registered node, half_clkin: n half_clkin!half_clkin n half_clkin clockclkin n half_clkin resetgnd n half_clkin setgnd moving to the down-counter, lets implement this simple 4-bit auto-reload down-counter, shown in figure 43. it will be clocked by half_clkin and its output zero will indicate when the count has reached zero, at which time the counter will automatically reload the initial value and count down again. the mcu will load an initial 4-bit value just once (during a startup initialization routine) and the counter will automatically reload this value as needed. the mcu loads the count by writing to four omcs that we have labeled init_count0 through init_count3. the mcu just has to write to the appropriate address offset inside psd control register space, csiop to load the omcs. see the data sheet for details on control register offsets and functions. figure 43. 4-bit auto-reloading down-counter lets make assignments for the clock, reset, and preset using the design assistant gui, but leave each node input equation blank (assignment will be made later when editing abel file). the down-c ounter will be clocked with the divided clock of figure 42. so make these assignments for the register nodes: down_count0, down_count1, down_count2, and down_count3. n down_countx 37/49 AN1356 - application note n inti_countx set gnd the clock and preset inputs are grounded because we do not want any logic overriding what the mcu has loaded into these registers. and finally, the combinatorial node, term_count needs no equation assigned from design assistant gui because it will be defined by adding statements to the abel file later. leave it blank. click done and you will exit the design assistant. at this time, an abel hdl file is generated and preliminary checks are performed. editing the generated abel hdl file click the box edit/add logic statements. you will see two windows pop up. the hdl assistant window is there for your easy reference. you may browse through it to find abel language examples for various declarations and logic functions. simply cut and paste the desired statements into the other window that has popped up, the psdabel design entry window. note that you may turn off the hdl assistant feature by pulling down preference from the top menu and un-checking the appropriate box. the psdabel design entry window is a text editor for the generated abel file. be careful to type only within the areas designated as preserved areas. if you type outside of these preserved areas, you will loose those statements next time psdsoft generates the abel file again after a design iteration in the design assistant gui. there are two preserved areas, one for declarations and another for logic equations denoted by the following: // begin user preserved declarations (not affected by iterations of da usage) type your declaration statements here // end user preserved declarations (not affected by iterations of da usage) // begin user preserved equations (not affected by iterations of da usage) type your logic equation statements here // end user preserved equations (not affected by iterations of da usage) for this example design, type in the following declarations: // begin user preserved declarations (not affected by iterations of da usage) =================== wsipsd property 'databus_omc d[7:4]:down_count[3:0]'; // this property statement forces the alignment of // down_count bits [3..0] to the mcu data bus bit positions [7..4]. // if this wsipsd property statement was not present, then psdsoft // would pick random mcu bit positions. the wsipsd property is needed // only if the mcu will read or write to microcells and only if a // particular mcu data bus position is required by the designer. AN1356 - application note 38/49 wsipsd property 'databus_omc d[3:0]:init_count[3:0]'; // this statement forces the alignment of // init_count bits [3..0] to the mcu data bus bit positions [3..0]. dcount = [down_count3..down_count0]; // 4-bit down counter init = [init_count3..init_count0];// 4-bit initial count from mcu stinputs = [strobed_in_7..strobed_in_0]; // 8 inputs that are stobed (sampled) on the way into // the psd (debounced). these inputs are clocked on the // opposite edge of the state machine clock (!clkin) so // they are stable for each state machine transition. state_machine = [state_bit_1..state_bit_0]; // 2 bits for 4-state state machine. clocked by // common psd clock input (clkin). // end user preserved declarations (not affected by iterations of da usage) =================== now type in the following equations for the down-counter and the state-machine: // begin user preserved equations (not affected by iterations of da usage) =================== //**** 4-bit down counter. accepts initial value from mcu, auto reloads **** term_count = (dcount.fb == 0); // true when count reaches zero when (term_count) then dcount := init; // automatically reload counter with initial // value after a count of zero is reached zero = term_count; // assign terminal count to psd output pin //**** simple state machine, looks for predefined sequence // of values appearing on the 8 strobed inputs ***** state_diagram state_machine; state 0: sequence_ok = 0; // indicate sequence not found yet if ((begin == 1) & (sys_ready == 1)) then 1 else 0; // stay in this state if 'begin' 39/49 AN1356 - application note // signal is zero or system is // not ready state 1: if (stinputs == ^hab) then 2 else 1; // stay in this state until pattern abh is found state 2: if (stinputs == ^hcd) then 3 else 2; // stay in this state until pattern cdh is found state 3: sequence_ok = 1; // indicate correct sequence was found, then start over goto 0; // end user preserved equations (not affected by iterations of da usage) =================== here is the representative state diagram of the state-machine: figure 44. example state machine finishing the design click the fit design to silicon box. after a successful fit, click the merge mcu firmware box, and follow the same procedure used in the first design. no firmware filename needs to be designated for the main psd flash memory segments (fs0 C fs7) since they will be programmed by the p51xa during iap. click ok in the merging screen to create a composite object file, logicxa.obj, for programming. you are now ready to program the psd as described in the section entitled programming the psd on page 21. ai04085 begin = 1 & sys_ready = 1 state 0 sequence_ok = 0 state 1 state 2 state 3 sequence_ok = 1 if inputs = 'ab' hex if inputs = 'cd' hex AN1356 - application note 40/49 third design example C isp and advanced iap the third design example adds enhanced iap features. the physical connections between the mcu and psd4235g2 do not change, but chip-selects (memory map) and psd page register definitions do change. we will not change any of the cpld logic in this design. this enhanced design derives the most utility out of the psd architecture by providing a means to replace the secondary psd flash memory with a segment of main psdflash memory (swapping) after iap is complete. these benefits result: n iap bootloader code in secondary psd flash memory can be updated in the field while executing from main psd flash memory. n the entire application can be executed from main flash memory after iap is complete. n the system software designer can make use of two sets of mcu interrupt vectors/routines and low-level code: one set during iap (contained in secondary flash memory) and a different set after iap (contained in main flash memory). n the secondary psd flash memory can be split in half. one half used for boot loader code during iap and the other half used as general data storage after iap. memory map the memory map for this design is a sequence of four steps shown in figure 45 through to figure 48. figure 45 is the memory map at system power-on or system reset. the swap bit and unlock bit are defined as two of the eight psd page register bits. heres the sequence after power-up or reset: n figure 45: p51xa boots from secondary flash memory (csboot0/csboot1) at address 0000, the vm register contains the initial value of 12h from the point-and-click settings in psdsoft. n figure 45: p51xa performs a checksum of main flash memory (fs0..fs7) in data space n figure 45: p51xa downloads to main flash memory from host computer if needed and validate contents n figure 45: p51xa writes 06h to psd vm register n figure 46: main flash memory has moved to program space because of 06h in vm register n figure 46: p51xa sets swap bit to logic one (writes to psd page register) n figure 47: secondary flash memory (csboot0/sboot1) has moved out of the mcu address range 0000 to 3fff and main flash memory (fs0) has moved into its place because of the swap bit. this swapping action is implemented by qualifying the chip-selects with the swap signal. also as a result of setting the swap bit, the secondary flash memory segments csboot2 and csboot3 appear. they cannot be used for data until after the next step. n figure 47: p51xa writes 0ch to psd vm register. n figure 48: secondary flash memory (csboot0..csboot3) has moved to data space because of 0ch in vm register. now secondary flash memory segments csboot2 and csboot3 can be used for general data. figure 48 shows the final memory map. the p51xa now has a full 512 kbytes of main flash memory (fs0 .. fs7) in program space, 16 kbytes secondary flash memory (csboot2/csboot3) in data space for general data storage, as well as 8 kbytes of battery backed sram (rs0) in data space. the 16 kbytes of iap loader code (csboot0/csboot1) is no longer in mcu executable position. if the p51xa needs to update the iap loader code that resides in secondary flash memory segments csboot0 and csboot1, it may do so only after setting the unlock bit in the page register. note that all page register bits are cleared to zero at power-on and at any system reset. 41/49 AN1356 - application note figure 45. memory map at boot-up or reset and during iap (1) note: 1. psd vm register initially 12h, main psd flash memory in data space. 2. iap loader code gets programmed here by jtag-isp or conventional programmer tool. 8ffffh 04000h 8ffffh 80000h 02000h - 03fffh 00000h - 01fffh 7ffffh 0ffffh 5ffffh 70000h 50000h 30000h 3ffffh ai04073 fs0 64k bytes psd main flash nothing mapped csboot0, 8kb psd 2nd flash csboot1, 8kb psd 2nd flash p51xa program space p51xa data space swap bit = 0 vm reg = 12h unlock bit = 0 (note 2) fs7 64k bytes psd main flash fs6 64k bytes psd main flash fs5 64k bytes psd main flash fs4 64k bytes psd main flash fs3 64k bytes psd main flash fs2 64k bytes psd main flash fs1 64k bytes psd main flash 10000h nothing mapped csiop, psd cnti regs rs0, 8k bytes psd sram nothing mapped lcd_e, ext lcd chip sel p51xa-g3 regs/sram 6ffffh 60000h 4ffffh 40000h 2ffffh 20000h 0a000h 08000h - 09fffh 07000h - 070ffh 06000h - 06001h 00400h - 05fffh 00000h - 003ffh 1ffffh 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes AN1356 - application note 42/49 figure 46. memory map just after p51xa writes 06h to psd vm register note: iap complete, main psd flash memory moves to program space 8ffffh 04000h 8ffffh 02000h - 03fffh 00000h - 01fffh ai04074 csboot0, 8kb psd 2nd flash csboot1, 8kb psd 2nd flash p51xa program space p51xa data space swap bit = 0 vm reg = 06h unlock bit = 0 nothing mapped csiop, psd cnti regs rs0, 8k bytes psd sram nothing mapped lcd_e, ext lcd chip sel p51xa-g3 regs/sram 0a000h 08000h - 09fffh 07000h - 070ffh 06000h - 06001h 00400h - 05fffh 00000h - 003ffh fs0 64k bytes psd main flash fs7 64k bytes psd main flash fs6 64k bytes psd main flash fs5 64k bytes psd main flash fs4 64k bytes psd main flash fs3 64k bytes psd main flash fs2 64k bytes psd main flash fs1 64k bytes psd main flash nothing mapped 80000h 7ffffh 0ffffh 5ffffh 70000h 50000h 30000h 3ffffh 10000h 6ffffh 60000h 4ffffh 40000h 2ffffh 20000h 1ffffh 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 43/49 AN1356 - application note figure 47. memory map just after p51xa sets swap bit = 1 note: iap loader code is swapped away, main psd flash memory takes its place.vm reg = 06, unlock = 0 7ffffh 88000h 8ffffh 82000h - 83fffh 80000h - 81fffh ai04075 csboot0, 8kb psd 2nd flash csboot1, 8kb psd 2nd flash p51xa program space p51xa data space nothing mapped csiop, psd cnti regs rs0, 8k bytes psd sram nothing mapped lcd_e, ext lcd chip sel p51xa-g3 regs/sram 0a000h 08000h - 09fffh 07000h - 070ffh 06000h - 06001h 00400h - 05fffh 00000h - 003ffh fs7 64k bytes psd main flash fs6 64k bytes psd main flash fs5 64k bytes psd main flash fs4 64k bytes psd main flash fs3 64k bytes psd main flash fs2 64k bytes psd main flash fs1 64k bytes psd main flash fs0 64k bytes psd main flash nothing mapped 70000h 6ffffh 8ffffh 4ffffh 60000h 40000h 20000h 2ffffh 00000h 5ffffh 50000h 3ffffh 30000h 1ffffh 10000h 0ffffh 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 84000h - 85fffh csboot2, 8kb psd 2nd flash 86000h - 87fffh csboot3, 8kb psd 2nd flash AN1356 - application note 44/49 figure 48. memory map just after p51xa writes 0ch to psd vm register (1) note: 1. secondary psd flash memory moves to data space. swap = 1, unlock = 0 2. iap loader code only accessible if unlock bit = 1. each time this p51xa system gets reset or goes through a power-on cycle, the psd presents the memory map of figure 45 to the mcu, and the boot sequence is repeated. note: when the p51xa is executing code from the secondary psd flash memory (csboot0 and csboot1), and then it sets the swap bit, it is very important that the p51xa firmware linker has set up synchronized code in the segment of main psd flash memory that replaces the secondary psd flash memory. this is necessary to create seamless mcu operation during the actual swap of memory since the p51xa is completely unaware that there is a swap going on. it just continues to fetch opcodes and operands during the memory swap. this requires that the operands and opcodes in main psd flash memory that follow the mcu instructions that actually set the swap bit in the secondary psd flash memory, are continuous. this means that the remainder of the instructions to complete setting the swap bit is present in main psd flash memory so there is continuous operation throughout the memory swapping process. 8ffffh 00000h 8ffffh ai04076 p51xa program space p51xa data space swap bit = 0 vm reg = 0ch unlock bit = 0 nothing mapped csiop, psd cnti regs rs0, 8k bytes psd sram nothing mapped lcd_e, ext lcd chip sel p51xa-g3 regs/sram 0a000h 08000h - 09fffh 07000h - 070ffh 06000h - 06001h 00400h - 05fffh 00000h - 003ffh fs7 64k bytes psd main flash fs6 64k bytes psd main flash fs5 64k bytes psd main flash fs4 64k bytes psd main flash fs3 64k bytes psd main flash fs2 64k bytes psd main flash fs1 64k bytes psd main flash fs0 64k bytes psd main flash nothing mapped 80000h 7ffffh 1ffffh 5ffffh 70000h 50000h 30000h 3ffffh 10000h 6ffffh 60000h 4ffffh 40000h 2ffffh 0ffffh 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes 64k bytes csboot0, 8kb psd 2nd flash csboot1, 8kb psd 2nd flash csboot0, 8kb psd 2nd flash csboot1, 8kb psd 2nd flash nothing mapped 20000h 86000h - 87fffh 84000h - 85fffh 82000h - 83fffh 80000h - 81fffh note (2) 45/49 AN1356 - application note psdsoft express design entry to implement the advanced memory maps of figure 45 through to figure 48, invoke psdsoft express , open the project logicxa from the second design example (if not already open). now pull down the menu project from the top of the screen, and select save as. for this third design example, save the second project under the new name advancxa. now click on the define psd pin/node functions box in the design flow diagram. click next >> to get to the page register definition screen since no pin assignments need to be changed for this third design. page register definition you will need to define two additional psd page register bits to be used for logic as shown below labeling one bit swap and the other bit unlock. figure 49. page register definition click next >> . chip-select equations the chip-select equations for psd sram (rs0), psd control registers (csiop), and the external lcd module (lcd_e), and most of the internal psd memory segments do not change from the second design example. only chip-selects for main psd flash memory segment fs0, and the secondary psd flash memory segments csboot0 C csboot3 need to change for this third design because they are affected by memory swapping. these internal memory chip-selects must be qualified with the page register bit swap as shown below. the secondary psd memory segments, csboot0 and csboot1, must be additionally qualified by unlock AN1356 - application note 46/49 to prevent the mcu from inadvertently writing to iap boot and loader code after iap is complete. the following illustrates how the chip-selects will look when you enter their definition based the memory maps of on figure 45 through to figure 48. figure 50. fs0 address range figure 51. csboot0 address range figure 52. csboot1 address range 47/49 AN1356 - application note figure 53. csboot2 address range figure 54. csboot3 address range notice that these psd physical memory segments can appear in more that one mcu address space depending on the swap and unlock qualifiers. now the memory maps of figure 45 through to figure 48 have been implemented. click done and you should see the main flow diagram. finishing the design theres no need to edit the the abel hdl statements since we have not touched the cpld. click the fit design to silicon box. after a successful fit, click the merge mcu firmware box. you will see an informational dialog box pop up that indicates non-natural address signals were used in psd chip-select equations. this is because of the swap and unlock bits. psdsoft displays this message to remind you that your mcu compiler/linker should account for any non-naturual mcu address signals. click ok , since this does not apply to our example. now specify the file name \psdsoft\examples\boot_16k.hex for segments csboot0 and csboot1. there is no p51xa firmware in this file, it is used only for illustration. you will find the pattern aah in csboot0, and the pattern bbh in csboot1. no firmware filename needs to be designated for the main psd flash memory segments (fs0 C fs7) since they will be programmed by the p51xa during iap. no firmware file needs to AN1356 - application note 48/49 be specified for secondary psd flash memory segments csboot2 and csboot3 because these will be used for general purpose data written by the p51xa. click ok in the merging screen to create a composite object file for programming. you are now ready to program the psd as described in the section entitled programming the psd on page 21. conclusion these examples are just three of an endless number of ways to configure the easy flash psd for your system. concurrent memories with a built-in programmable decoder at the segment level offer excellent flexibility. the ability to expand your system does not require any physical connection changes, as everything is configured internal to the psd. and finally, the jtag channel can be used for isp anytime, and anywhere, with no participation from the mcu. all of these features are crosschecked under the psdsoft express ? development environment to minimize your effort to design a flash memory-based system capable of isp and iap. references 1. psd4235g2 data sheet 2. application note an1153 jtag informationpsd8xxf for detailed use of the jtag channel 49/49 AN1356 - application note for current information on psd products, please consult our pages on the world wide web: www.st.com/psd if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2001 stmicroelectronics - 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